An Integrated Fault-Tolerant Design Framework for VLIW Processors

In this study, a fault-tolerant design framework of VLIW processor is proposed. Specifically, this paper concentrates on the issue of dependable data path design. We first use three identical functional modules in the data paths to demonstrate our fault-tolerant technique. Basically, we add one spare module in this illustration and refine on the concepts of triple modular redundancy and comparison to achieve fault detection, fault location and error recovery. A real-time error recovery process is developed to conquer the faults. Hardware architecture and its implementation in VHDL are presented. The analysis of hardware overhead and performance degradation is conducted to validate our scheme. We show that the proposed scheme can be easily extended to data paths, which contains more than three identical functional modules. In addition, for a specific number of identical modules, the fault-tolerant framework provides a design choice among several feasible solutions in terms of hardware overhead, performance degradation and dependability requirements. Finally, hardware overhead and performance degradation of the proposed technique decreases while the number of identical modules increases in the data path of VLIW processors.